By Arndt Bode (auth.), Ming Xu, Yinwei Zhan, Jiannong Cao, Yijun Liu (eds.)
We are at present witnessing a proliferation in parallel and disbursed processing applied sciences and purposes. although, extra new applied sciences have ushered in unprecented demanding situations to the learn group around the diversity of high-performance computing, multi-core microprocessor structure, networks and pervasive computing, in addition to new paradigm computing matters. APPT 2007 was once subsidized by way of the China computing device Federation, in cooperation with TCPP of the Institute for electric and Electronics Engineers (IEEE). The hugely confident responses to the former APPT workshops inspired us to proceed this overseas occasion. This yr, APPT was once upgraded to the foreign Symposium on complicated Parallel Processing applied sciences. even if, it saved its conventional style via sharing of the underlying theories and purposes, and the institution of latest and long term collaborative channels. and it'll proceed to supply a discussion board for researchers, pros, and commercial practitioners from all over the world to file on new advances in high-performance structure and software program, in addition to to spot matters and instructions for learn and improvement within the new period of evolving applied sciences. The luck of APPT 2007 used to be end result of the the exertions and making plans of a big workforce of well known researchers from around the globe, who served at the Technical application Committee and the Organizing Committee. Their worthy efforts in constructing this technical software are such a lot gratefully said. specifically, we wish to thank this system Co-chairs, Xin Chen, Xuejun Yang, and Albert Y. Zomaya.
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Additional info for Advanced Parallel Processing Technologies: 7th International Symposium, APPT 2007 Guangzhou, China, November 22-23, 2007 Proceedings
CPU0 saw after 4 kinds of signals CPU0 periodically sent impulse signal wdi0 to WDT0, denoting that CPU0 works normally. CPU0 received nRESET from WDT0, in order to reset CPU0 and resume from fault state. CPU0 received IS0 from WDT1 to take over the system when CPU1 had been broken. CPU0 received MS0 simultaneously from arbitrator, in order to judge the respective current state of CPU0 and CPU1. ① ② ③ ④ B. WDT0 took charge into inspecting CPU0 After the system had been electrified, CPU0 periodically sent WDT0 an impulse signal wdi0, which reset the counter of WDT0 to 0.
Research on Realizationof ASIC in Chinese Spacecraft. Chinese Space Science and Technology 5 (2002) 2. : Analyzing SEU Effects in SRAM-based FPGAs. IOLTS2003: IEEE International On-Line Testing Symposium , 119–123 (2003) 3. : Improving FPGA Design Robustness with Partial TMR. C. (September 2005) 4. : Mitigation techniques for electronics in Single Event Upset environments[EB/OL]. US: Opensystems Publishing, Military Embedded Systems, [2006-6-27]. com/articles/authors/lai 5. : The Fault Tolerant System Design of Housekeeping Computer for small satellite.
Combined with the system architecture and needs of the design, we put forward a design scheme of COTS-based multi-level fault-tolerant architecture, and finally used an analytical model to validate the reliability of the design. 2 Architecture The COTS-based space computer system architecture is shown in figure 1. The COTS-based chips of the system like SRAM, Flash, CPU and so on, are all prone to suffer from SEU, and consequently result in bad working status. M. Xu et al. ): APPT 2007, LNCS 4847, pp.
Advanced Parallel Processing Technologies: 7th International Symposium, APPT 2007 Guangzhou, China, November 22-23, 2007 Proceedings by Arndt Bode (auth.), Ming Xu, Yinwei Zhan, Jiannong Cao, Yijun Liu (eds.)